Author of the publication

Predicting User Perception Regarding Usefulness of Google Classroom Through Machine Learning Algorithms.

, , , and . ICCCNT, page 1-5. IEEE, (2023)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A Comparative Study of Different Transfer Learning Models for Classification of Urban Manhole States., , , , , and . ICCTA, page 25-30. IEEE, (2022)A combined all-digital PLL-buck slack regulation system with autonomous CCM/DCM transition control and 82% average voltage-margin reduction in a 0.6-to-1.0V cortex-M0 processor., , , , , , and . ISSCC, page 302-304. IEEE, (2018)Computationally Enabled Total Energy Minimization Under Performance Requirements for a Voltage-Regulated 0.38-to-0.58V Microprocessor in 65nm CMOS., , , , and . ISSCC, page 312-314. IEEE, (2019)A Unified Clock and Switched-Capacitor-Based Power Delivery Architecture for Variation Tolerance in Low-Voltage SoC Domains., , , , , , , and . IEEE J. Solid State Circuits, 54 (4): 1173-1184 (2019)Multiple Skin-Disease Classification Based on Machine Vision Using Transfer Learning Approach., , , and . ICCCNT, page 1-8. IEEE, (2023)An All-Digital Unified Clock Frequency and Switched-Capacitor Voltage Regulator for Variation Tolerance in a Sub-Threshold ARM Cortex M0 Processor., , , , , , , and . VLSI Circuits, page 65-66. IEEE, (2018)An All-Digital Fused PLL-Buck Architecture for 82% Average Vdd-Margin Reduction in a 0.6-to-1.0-V Cortex-M0 Processor., , , , , , and . IEEE J. Solid State Circuits, 54 (11): 3215-3225 (2019)A 1-2 GHz Computational-Locking ADPLL With Sub-20-Cycle Locktime Across PVT Variation., , and . IEEE J. Solid State Circuits, 54 (9): 2487-2500 (2019)A Comparative Study on Road Surface State Assessment Using Transfer Learning Approach., , , , and . ICCCNT, page 1-6. IEEE, (2022)An All-Digital True-Random-Number Generator with Integrated De-correlation and Bias Correction at 3.2-to-86 MB/S, 2.58 PJ/Bit in 65-NM CMOS., , , , , and . VLSI Circuits, page 1-2. IEEE, (2018)