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Prototyping Efficient Interprocessor Communication Mechanisms., , , , , , , , and . ICSAMOS, page 26-33. IEEE, (2007)Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior., , , and . MICRO, page 65-76. IEEE Computer Society, (2010)FIST: A fast, lightweight, FPGA-friendly packet latency estimator for NoC modeling in full-system simulations., , and . NOCS, page 137-144. ACM/IEEE Computer Society, (2011)Prototype and evaluation of the CoRAM memory architecture for FPGA-based computing., , , , and . FPGA, page 139-142. ACM, (2012)Fast scalable FPGA-based Network-on-Chip simulation models.. MEMOCODE, page 77-82. IEEE, (2011)A Configurable Cloud-Scale DNN Processor for Real-Time AI., , , , , , , , , and 10 other author(s). ISCA, page 1-14. IEEE Computer Society, (2018)CONNECT: re-examining conventional wisdom for designing nocs in the context of FPGAs., and . FPGA, page 37-46. ACM, (2012)Cross-platform FPGA accelerator development using CoRAM and CONNECT., , , and . FPGA, page 3-4. ACM, (2013)Towards automatic customization of interconnect and memory in the CoRAM abstraction (abstract only)., and . FPGA, page 265. ACM, (2013)HPC on FPGA clouds: 3D FFTs and implications for molecular dynamics., , , , , and . FPL, page 1-4. IEEE, (2017)