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Disambiguation of "de Gyvez, José Pineda"

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Timing Speculation With Optimal In Situ Monitoring Placement and Within-Cycle Error Prevention.

, , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (5): 1206-1217 (2019)

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José Robinson Ramírez Pineda

José Guillermo De Aguinaga

Humberto Jorge José

Nadine José Gonzalez

Marcos Pineda

 

Other publications of authors with the same name

VDD Ramp Testing for RF Circuits., , and . ITC, page 651-658. IEEE Computer Society, (2003)Integrated circuit defect-sensitivity - theory and computational models.. The Kluwer international series in engineering and computer science Kluwer, (1993)Preprocessing operators for image compression using cellular neural networks., and . ICNN, page 1500-1505. IEEE, (1996)On the design and implementation of a wafer yield editor., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 8 (8): 920-925 (1989)Limits to performance spread tuning using adaptive voltage and body biasing., , and . ISCAS (1), page 5-8. IEEE, (2005)Standard cell library tuning for variability tolerant designs., , , and . DATE, page 1-6. European Design and Automation Association, (2014)Low energy FPGA interconnect design., , and . ACM Great Lakes Symposium on VLSI, page 393-396. ACM, (2004)Slack-aware timing margin redistribution technique utilizing error avoidance flip-flops and time borrowing., , , and . VLSI-SoC, page 159-164. IEEE, (2015)Built-in Current Sensor for ?IDDQ Testing of Deep Submicron Digital CMOS ICs., and . VTS, page 53-58. IEEE Computer Society, (2004)A layout defect-sensitivity extractor., and . ICCAD, page 538-541. IEEE Computer Society, (1989)