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Design and FPGA Prototyping of a H.264/AVC Main Profile., , , , , , , , and . J. Braz. Comput. Soc., 13 (1): 25-36 (2007)AxPPA: Approximate Parallel Prefix Adders., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 31 (1): 17-28 (2023)Exploring NLMS-Based Adaptive Filter Hardware Architectures for Eliminating Power Line Interference in EEG Signals., , , , , , and . Circuits Syst. Signal Process., 40 (7): 3305-3337 (2021)Robustness Analysis of 3-2 Adder Compressor Designed in 7-nm FinFET Technology., , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 70 (3): 1264-1268 (March 2023)A Framework for Crossing Temperature-Induced Timing Errors Underlying Hardware Accelerators to the Algorithm and Application Layers., , , , , , and . IEEE Trans. Computers, 71 (2): 349-363 (2022)Energy-Throughput Configurable Design for Video Processing Binary Arithmetic Encoder., , , and . IEEE Trans. Circuits Syst. Video Technol., 31 (3): 1163-1177 (2021)A Cross-Layer Gate-Level-to-Application Co-Simulation for Design Space Exploration of Approximate Circuits in HEVC Video Encoders., , , , , and . IEEE Trans. Circuits Syst. Video Technol., 30 (10): 3814-3828 (2020)A DC offset and CMRR analysis in a CMOS 0.35 µm operational transconductance amplifier using Pelgrom's area/accuracy tradeoff., and . Microelectron. J., 40 (9): 1281-1292 (2009)A tool for automatic design of analog circuits based on gm/ID methodology., , and . ISCAS, IEEE, (2006)Improving devices communication in Industry 4.0 wireless networks., , , , , and . Eng. Appl. Artif. Intell., (2019)