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Logarithmic AD conversion using latched comparators and a time-to-digital converter., , and . ICECS, page 319-322. IEEE, (2014)SCALES: A high speed simulator tool for pipeline A/D converters., , and . SMACD, page 1-4. IEEE, (2016)Overcurrent detection circuit for integrated class-D amplifiers., , , and . ECCTD, page 401-404. IEEE, (2011)Automatic technology migration of analog IC designs using generic cell libraries., , , , and . DATE, page 1281-1284. IEEE, (2017)A true logarithmic analog-to-digital pipeline converter with 1.5 bit/stage and digital correction., , and . ICECS, page 393-396. IEEE, (2001)An evolutionary optimization kernel using a dynamic GA-SVM model applied to analog IC design., , and . ECCTD, page 32-35. IEEE, (2007)A reconfigurable A/D converter for 4G wireless systems., , and . ISCAS, page 924-927. IEEE, (2008)GA-SVM Optimization Kernel applied to Analog IC Design Automation., , and . ICECS, page 486-489. IEEE, (2006)Digitally-Controlled Analogue Signal Processing and Conversion Techniques Employing a Logarithmic Building Block., and . ISCAS, page 377-380. IEEE, (1994)A 20 DB Gain Two-Stage Low-Noise Amplifier with High Yield for 5 GHz Applications., , , , , and . SMACD, page 1-4. IEEE, (2018)