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Preventing timing errors on register writes: mechanisms of detections and recoveries.

, , , and . SIGARCH Comput. Archit. News, 35 (5): 25-31 (2007)

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Address Order Violation Detection with Parallel Counting Bloom Filters., , , and . IEICE Trans. Electron., 98-C (7): 580-593 (2015)Improvement of message communication in concurrent logic language., , , , , and . PASCO, page 156-164. ACM, (1997)Low-Overhead Architecture for Security Tag., , , , and . PRDC, page 135-142. IEEE Computer Society, (2009)String-Wise Information Flow Tracking against Script Injection Attacks., , , and . PRDC, page 169-176. IEEE Computer Society, (2009)Base Address Recognition with Data Flow Tracking for Injection Attack Detection., , , , , , and . PRDC, page 165-172. IEEE Computer Society, (2006)Efficient Goal Scheduling in Concurrent Logic Language using Type-Based Dependency Analysis., , , , , and . ASIAN, volume 1345 of Lecture Notes in Computer Science, page 268-282. Springer, (1997)An Analysis and a Solution of False Conflicts for Hardware Transactional Memory., , , , , and . ICECS, page 529-532. IEEE, (2018)A Technique to Eliminate Redundant Inter-Processor Communication on Parallelizing Compiler TINPAR., , , , , , and . Int. J. Parallel Program., 27 (2): 97-109 (1999)FXA: Executing Instructions in Front-End for Energy Efficiency., , , and . IEICE Trans. Inf. Syst., 99-D (4): 1092-1107 (2016)Low-Complexity Bypass Network Using Small RAM., , , , , and . CDES, page 153-159. CSREA Press, (2008)