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Disambiguation of "Perrott, Michael H."

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A Low-Noise, Wide-BW 3.6GHz Digital ΔΣ Fractional-N Frequency Synthesizer with a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation.

, , and . ISSCC, page 340-341. IEEE, (2008)

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Michael H Schoenberg

Michael H Stieglitz

Michael H Holthausen

Michael H Thung

Michael H Bischof

 

Other publications of authors with the same name

A clockless, multi-stable, CMOS analog circuit., and . ISCAS, page 1764-1767. IEEE, (2014)Session 15 overview: Data converter techniques., and . ISSCC, page 266-267. IEEE, (2013)Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuits.. DAC, page 498-503. ACM, (2002)A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation., , and . IEEE J. Solid State Circuits, 32 (11): 2048-2060 (1997)A Low-Noise, Wide-BW 3.6GHz Digital ΔΣ Fractional-N Frequency Synthesizer with a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation., , and . ISSCC, page 340-341. IEEE, (2008)A temperature-to-digital converter for a MEMS-based programmable oscillator with better than ±0.5ppm frequency stability., , , , , , , , , and 3 other author(s). ISSCC, page 206-208. IEEE, (2012)A 0.5V <4µW CMOS photoplethysmographic heart-rate sensor IC based on a non-uniform quantizer., , and . ISSCC, page 384-385. IEEE, (2013)A fractional- N frequency synthesizer architecture utilizing a mismatch compensated PFD/DAC structure for reduced quantization-induced phase noise., and . IEEE Trans. Circuits Syst. II Express Briefs, 50 (11): 839-849 (2003)A numerical design approach for high speed, differential, resistor-loaded, CMOS amplifiers., and . ISCAS (5), page 508-511. IEEE, (2004)A VCO-based Analog-to-digital Converter with Second-order Sigma-Delta Noise Shaping., and . ISCAS, page 3130-3133. IEEE, (2009)