( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
CMOS-on-quartz pulse generator for low power applications.

, , , , и . ASP-DAC, стр. 29-30. IEEE, (2017)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Toru Nomura

Toru Matsuyama

Toru Kashima

Richard Heinrich Torunsky

Ahmet Refah Torun

 

Другие публикации лиц с тем же именем

Power supply impedance emulation to eliminate overkills and underkills due to the impedance difference between ATE and customer board., , , , , , и . ITC, стр. 1-8. IEEE, (2016)An all-digital time difference hold-and-replication circuit utilizing a dual pulse ring oscillator., , , и . CICC, стр. 1-4. IEEE, (2013)On-chip resonant supply noise reduction utilizing switched parasitic capacitors of sleep blocks with tri-mode power gating structure., , , , , и . ESSCIRC, стр. 183-186. IEEE, (2011)A Pulse Width controlled PLL and its automated design flow., , , и . ICECS, стр. 5-8. IEEE, (2013)Optimal Design Method of Sub-Ranging ADC Based on Stochastic Comparator., , , и . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 101-A (2): 410-424 (2018)Extension of power supply impedance emulation method on ATE for multiple power domain., , , , , , и . ETS, стр. 1-2. IEEE, (2017)Buffer-ring-based all-digital on-chip monitor for PMOS and NMOS process variability and aging effects., , и . DDECS, стр. 167-172. IEEE Computer Society, (2010)Analytical design optimization of sub-ranging ADC based on stochastic comparator., , , и . DATE, стр. 517-522. IEEE, (2016)Density Aware Cell Library Design for Design-Technology Co-Optimization., и . ISQED, стр. 1. IEEE, (2022)Cascaded Time Difference Amplifier with Differential Logic Delay Cell., , , , и . IEICE Trans. Electron., 94-C (4): 654-662 (2011)