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A Methodology for Speeding Up Fast Fourier Transform Focusing on Memory Architecture Utilization.

, , , , , and . IEEE Trans. Signal Process., 59 (12): 6217-6226 (2011)

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High-performance FPGA implementations of the cryptographic hash function JH., , , and . IET Comput. Digit. Tech., 7 (1): 29-40 (2013)Throughput Optimization of the Cipher Message Authentication Code., , , and . DSP, page 495-498. IEEE, (2007)Evolution of the e-Museum Concept through Exploitation of Cryptographic Algorithms., , , and . EuroMed, volume 7616 of Lecture Notes in Computer Science, page 291-300. Springer, (2012)High performance pipelined FPGA implementation of the SHA-3 hash algorithm., , and . MECO, page 68-71. IEEE, (2015)Pipelined SHA-3 Implementations on FPGA: Architecture and Performance Analysis., , and . CS2@HiPEAC, page 13-18. ACM, (2015)High-throughput Hardware Architectures of the JH Round-three SHA-3 Candidate - An FPGA Design and Implementation Approach., , , , , and . SECRYPT, page 126-135. SciTePress, (2012)Efficient implementation of the keyed-hash message authentication code (HMAC) using the SHA-1 hash function., , , and . ICECS, page 567-570. IEEE, (2004)VLSI design and implementation of reconfigurable cryptographic systems for symmetric encryption., , , and . ICECS, page 1-4. IEEE, (2005)Server side hashing core exceeding 3 Gbps of throughput., , , , and . Int. J. Secur. Networks, 2 (3/4): 228-238 (2007)Temporal and System Level Modifications for High Speed VLSI Implementations of Cryptographic Core., , , , , and . ICECS, page 1180-1183. IEEE, (2006)