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Impact of Power Distribution Network on Power Analysis Attacks in Three-Dimensional Integrated Circuits.

, , , , and . ACM Great Lakes Symposium on VLSI, page 327-332. ACM, (2017)

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Power Distribution in TSV-Based 3-D Processor-Memory Stacks., and . IEEE J. Emerg. Sel. Topics Circuits Syst., 2 (4): 692-703 (2012)Noise coupling due to through silicon vias (TSVs) in 3-D integrated circuits.. ISCAS, page 1411-1414. IEEE, (2011)Design space exploration for robust power delivery in TSV based 3-D systems-on-chip., and . SoCC, page 307-311. IEEE, (2012)Impact of Power Distribution Network on Power Analysis Attacks in Three-Dimensional Integrated Circuits., , , , and . ACM Great Lakes Symposium on VLSI, page 327-332. ACM, (2017)FinFET-Based Low-Swing Clocking., , , , and . JETC, 12 (2): 13:1-13:20 (2015)Signal Shaping at Interface of Wireless Power Harvesting and AC Computational Logic., , , and . ISCAS, page 1-5. IEEE, (2019)Effect of TSV fabrication technology on power distribution in 3D ICs., and . ACM Great Lakes Symposium on VLSI, page 287-292. ACM, (2013)Efficient characterization of TSV-to-transistor noise coupling in 3D ICs., , and . ACM Great Lakes Symposium on VLSI, page 71-76. ACM, (2013)Shielding Methodologies in the Presence of Power/Ground Noise., , and . ISCAS, page 2277-2280. IEEE, (2009)Quantifying the effect of local interconnects on on-chip power distribution., and . Microelectron. J., 46 (3): 258-264 (2015)