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mm2 in-Memory Analog Matrix-Vector-Multiplier for DNN Acceleration.

I. Papistas, S. Cosemans, B. Rooseleer, J. Doevenspeck, M. Na, A. Mallik, P. Debacker, and D. Verkest. CICC, page 1-2. IEEE, (2021)

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Stephan Mallik

Arindam Chatterjee

Arindam Khan

Mohammed Nazmul Ahsan Mallik

Samir Ansari {Arindam Ghosal, Vikash Kumar}

Other publications of authors with the same name

The user in experimental computer systems research.P. Dinda, G. Memik, R. Dick, B. Lin, A. Mallik, A. Gupta, and S. Rossoff. Experimental Computer Science, page 10. ACM, (2007)Design and implementation of correlating caches.A. Mallik, M. Wildrick, and G. Memik. ISLPED, page 58-61. ACM, (2004)Variable latency caches for nanoscale processor.S. Ozdemir, A. Mallik, J. Ku, G. Memik, and Y. Ismail. SC, page 20. ACM Press, (2007)FQ-Conv: Fully Quantized Convolution for Efficient and Accurate Inference.B. Verhoef, N. Laubeuf, S. Cosemans, P. Debacker, I. Papistas, A. Mallik, and D. Verkest. CoRR, (2019)Smart bit-width allocation for low power optimization in a systemc based ASIC design environment.A. Mallik, D. Sinha, P. Banerjee, and H. Zhou. DATE, page 618-623. European Design and Automation Association, Leuven, Belgium, (2006)User- and process-driven dynamic voltage and frequency scaling.B. Lin, A. Mallik, P. Dinda, G. Memik, and R. Dick. ISPASS, page 11-22. IEEE Computer Society, (2009)Engineering Over-Clocking: Reliability-Performance Trade-Offs for High-Performance Register Files.G. Memik, M. Chowdhury, A. Mallik, and Y. Ismail. DSN, page 770-779. IEEE Computer Society, (2005)Performance Modeling and Workload Analysis of Distributed Large Language Model Training and Inference.J. Kundu, W. Guo, A. BanaGozar, U. Alwis, S. Sengupta, P. Gupta, and A. Mallik. CoRR, (2024)SAfEPaTh: A System-Level Approach for Efficient Power and Thermal Estimation of Convolutional Neural Network Accelerator.Y. Chen, S. Yang, D. Bhattacharjee, F. Catthoor, and A. Mallik. CoRR, (2024)Analog In-memory Computing in FeFET-based 1T1R Array for Edge AI Applications.D. Saito, T. Kobayashi, H. Koga, N. Ronchi, K. Banerjee, Y. Shuto, J. Okuno, K. Konishi, L. Piazza, A. Mallik and 5 other author(s). VLSI Circuits, page 1-2. IEEE, (2021)

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Disambiguation of "Mallik, Arindam"

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A 22 nm, 1540 TOP/s/W, 12.1 TOP/s/mm2 in-Memory Analog Matrix-Vector-Multiplier for DNN Acceleration.

Please choose a person to relate this publication to

Stephan Mallik

Arindam Chatterjee

Arindam Khan

Mohammed Nazmul Ahsan Mallik

Samir Ansari {Arindam Ghosal, Vikash Kumar}

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Mallik, Arindam"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 22 nm, 1540 TOP/s/W, 12.1 TOP/s/mm2 in-Memory Analog Matrix-Vector-Multiplier for DNN Acceleration.

Please choose a person to relate this publication to

Stephan Mallik

Arindam Chatterjee

Arindam Khan

Mohammed Nazmul Ahsan Mallik

Samir Ansari {Arindam Ghosal, Vikash Kumar}

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 22 nm, 1540 TOP/s/W, 12.1 TOP/s/mm2 in-Memory Analog Matrix-Vector-Multiplier for DNN Acceleration.