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Disambiguation of "Lai, Chang-Ming"

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28.3 A frequency-defined vernier digital-to-time converter for impulse radar systems in 65nm CMOS.

, , , , , and . ISSCC, page 474-475. IEEE, (2014)

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Ming-chien Chang

Ming-Chang Shih

Chang-Sheng Ming

Ming-Yen Chang

Chih-ming Chang

 

Other publications of authors with the same name

A UWB IR timed-array radar using time-shifted direct-sampling architecture., , , , , , , , , and 3 other author(s). VLSIC, page 54-55. IEEE, (2012)A mixed-signal phase-domain FSK demodulator for BLE single-path low-IF receiver., , , , and . VLSI-DAT, page 1-4. IEEE, (2014)An OPLL-DDS based frequency synthesizer for DCS-1800 receiver., , , and . ISCAS, IEEE, (2006)28.3 A frequency-defined vernier digital-to-time converter for impulse radar systems in 65nm CMOS., , , , , and . ISSCC, page 474-475. IEEE, (2014)A 90nm CMOS, 5.6ps, 0.23pJ/code time-to-digital converter with multipath oscillator and seamless cycle detection., , , and . A-SSCC, page 357-360. IEEE, (2011)A scalable direct-sampling broadband radar receiver supporting simultaneous digital multibeam array in 65nm CMOS., , , and . ISSCC, page 242-243. IEEE, (2013)A 0.24 to 2.4 GHz phase-locked loop with low supply sensitivity in 0.18-µm CMOS., , , , and . ISCAS, page 981-984. IEEE, (2011)A low-power CMOS LNA using noise suppression and distortion cancellation techniques with inductive bandwidth extension., , , and . ISOCC, page 120-123. IEEE, (2011)10.4 A 4×4 Dual-Band Dual-Concurrent WiFi 802.11ax Transceiver with Integrated LNA, PA and T/R Switch Achieving +20dBm 1024-QAM MCS11 Pout and -43dB EVM Floor in 55nm CMOS., , , , , , , , , and 7 other author(s). ISSCC, page 178-180. IEEE, (2020)Time-domain analog-to-digital converters with domino delay lines., , and . VLSI-DAT, page 1-4. IEEE, (2013)