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Disambiguation of "Cristal, Adrián"

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Thread Lock Section-Aware Scheduling on Asymmetric Single-ISA Multi-Core.

, , , , and . IEEE Comput. Archit. Lett., 14 (2): 160-163 (2015)

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Adrián Granada

Adrián Juárez

Adrián Navigante

Adrián Vergara Durán

Adrián Cartín-Valverde

 

Other publications of authors with the same name

A partitioned instruction queue to reduce instruction wakeup energy., , , , and . Int. J. High Perform. Comput. Netw., 1 (4): 153-161 (2004)The Velox Transactional Memory Stack., , , , , , , , , and 14 other author(s). IEEE Micro, 30 (5): 76-87 (2010)A Deep Learning Mapper (DLM) for Scheduling on Heterogeneous Systems., , , , , , and . CARLA, volume 796 of Communications in Computer and Information Science, page 3-20. Springer, (2017)VALib and SimpleVector: tools for rapid initial research on vector architectures., , , , , and . Conf. Computing Frontiers, page 7:1-7:10. ACM, (2014)Dynamic transaction coalescing., , , , , , and . Conf. Computing Frontiers, page 18:1-18:10. ACM, (2014)RMS-TM: a comprehensive benchmark suite for transactional memory systems., , , , , and . ICPE, page 335-346. ACM, (2011)Stand-Alone Memory Controller for Graphics System., , , , , , and . ARC, volume 8405 of Lecture Notes in Computer Science, page 108-120. Springer, (2014)Transactional Memory: An Overview., , , , , , and . IEEE Micro, 27 (3): 8-29 (2007)On the selection of adder unit in energy efficient vector processing., , , , , and . ISQED, page 143-150. IEEE, (2013)Implications of non-volatile memory as primary storage for database management systems., , , , and . SAMOS, page 164-171. IEEE, (2016)