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Disambiguation of "Kobayashi, Kazutoshi"

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Impact of random telegraph noise on ring oscillators evaluated by circuit-level simulations.

, , , , and . ICICDT, page 1-4. IEEE, (2015)

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Kazutoshi Miyazawa

Yoshitake Kobayashi

Wakiko Kobayashi

Wataru Kobayashi

Makoto Kobayashi

 

Other publications of authors with the same name

Evaluation of FPGA design guardband caused by inhomogeneous NBTI degradation considering process variations., and . FPT, page 417-420. IEEE, (2010)Circuit-level simulation methodology for Random Telegraph Noise by using Verilog-AMS., , , , , and . ICICDT, page 1-4. IEEE, (2017)Cost-Effective Test Screening Method on 40-nm Embedded SRAMs for Low-Power MCUs., , , and . IEEE Trans. Very Large Scale Integr. Syst., 29 (7): 1495-1499 (2021)An Analysis of Local BTI Variation with Ring-Oscillator in Advanced Processes and Its Impact on Logic Circuit and SRAM., , , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 104-A (11): 1536-1545 (2021)A Bit-Error Rate Measurement and Error Analysis of Wireline Data Transmission using Current Source Model for Single Event Effect under Irradiation Environment., , , , and . J. Electron. Test., 37 (5): 675-684 (2021)Correlations between BTI-Induced Degradations and Process Variations on ASICs and FPGAs., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 97-A (12): 2367-2372 (2014)A Comprehensive Simulation and Test Environment for Prototype VLSI Verification., and . IEICE Trans. Inf. Syst., 87-D (3): 630-636 (2004)An Efficient and Accurate Time Step Control Method for Power Device Transient Simulation Utilizing Dominant Time Constant Approximation., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (2): 451-463 (2020)Disturbance Aware Dynamic Power Reduction in Synchronous 2RW Dual-Port 8T SRAM by Self-Adjusting Wordline Pulse Timing., , , , and . IEEE J. Solid State Circuits, 58 (7): 2098-2108 (2023)Characterizing SRAM and FF soft error rates with measurement and simulation., , , , and . Integr., (2019)