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RosettaStone: Connecting the Past, Present, and Future of Physical Design Research.

, , , and . IEEE Des. Test, 39 (5): 70-78 (2022)

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Toward better wireload models in the presence of obstacles., , , and . IEEE Trans. Very Large Scale Integr. Syst., 10 (2): 177-189 (2002)Enhanced Power Delivery Pathfinding for Emerging 3-D Integration Technology., , , and . IEEE Trans. Very Large Scale Integr. Syst., 29 (4): 591-604 (2021)Detailed Placement for Enhanced Control of Resist and Etch CDs., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (12): 2144-2157 (2007)Fast Hypergraph Partition.. DAC, page 762-766. ACM Press, (1989)Rectilinear Steiner Trees with Minimum Elmore Delay., , , and . DAC, page 381-386. ACM Press, (1994)Multilevel Circuit Partitioning., , and . DAC, page 530-533. ACM Press, (1997)Hypergraph Partitioning with Fixed Vertices., , and . DAC, page 355-359. ACM Press, (1999)Analysis of RC interconnections under ramp input., and . ACM Trans. Design Autom. Electr. Syst., 2 (2): 168-192 (1997)A semi-persistent clustering technique for VLSI circuit placement., , , , and . ISPD, page 200-207. ACM, (2005)Co-optimization of memory BIST grouping, test scheduling, and logic placement., and . DATE, page 1-6. European Design and Automation Association, (2014)