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An Overview of Dedicated Hardware Designs for State-of-the-Art AV1 and H.266/VVC Video Codecs.

, , , , , , и . ICECS, стр. 1-4. IEEE, (2020)

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Fritz Zattler

Peter Zattler

Bernd Zattler

Jürgen Zattler

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Другие публикации лиц с тем же именем

Speedup-aware history-based tiling algorithm for the HEVC standard., , , и . ICIP, стр. 824-828. IEEE, (2016)AV1 and VVC Video Codecs: Overview on Complexity Reduction and Hardware Design., , , , , , , и . IEEE Open J. Circuits Syst., (2021)Power efficient and high troughtput multi-size IDCT targeting UHD HEVC decoders., , , , , и . ISCAS, стр. 1925-1928. IEEE, (2014)A Low-Area and High-Throughput Intra Prediction Architecture for a Multi-Standard HEVC and H.264/AVC Video Encoder., , , и . SBCCI, стр. 10:1-10:6. ACM, (2015)Low-power HEVC binarizer architecture for the CABAC block targeting UHD video processing., , , , и . SBCCI, стр. 30-35. ACM, (2017)Novel multiple bypass bins scheme for low-power UHD video processing HEVC binary arithmetic encoder architecture., , , и . SBCCI, стр. 47-52. ACM, (2017)Real-Time Architecture for HEVC Motion Compensation Sample Interpolator for UHD Videos., , , , и . SBCCI, стр. 12:1-12:6. ACM, (2015)Memory Hierarchy Targeting Bi-Predictive Motion Compensation for H.264/AVC Decoder., , , , и . ISVLSI, стр. 445-446. IEEE Computer Society, (2007)A high throughput CAVLC hardware architecture with parallel coefficients processing for HDTV H.264/AVC enconding., , , , и . ICECS, стр. 587-590. IEEE, (2010)A low-power memory architecture with application-aware power management for motion & disparity estimation in Multiview Video Coding., , , и . ICCAD, стр. 40-47. IEEE Computer Society, (2011)