( en | de | ru )

 

Disambiguation of "Jaleel, Aamer"

Author of the publication

copydeleteadd this publication to your clipboard
Accelerating Sparse Data Orchestration via Dynamic Reflexive Tiling.

, , , , , , , , , , and . ASPLOS (3), page 18-32. ACM, (2023)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Jaleel Akhtar

Hassan Jaleel

 

Other publications of authors with the same name

Mind The Power Holes: Sifting Operating Points in Power-Limited Heterogeneous Multicores., , , and . IEEE Comput. Archit. Lett., 16 (1): 56-59 (2017)P-OPT: Practical Optimal Cache Replacement for Graph Analytics., , , and . HPCA, page 668-681. IEEE, (2021)RIC: Relaxed Inclusion Caches for Mitigating LLC Side-Channel Attacks., , , , , , and . DAC, page 7:1-7:6. ACM, (2017)Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions., and . HPCA, page 191-200. IEEE Computer Society, (2005)In-Line Interrupt Handling for Software-Managed TLBs., and . ICCD, page 62-67. IEEE Computer Society, (2001)BEAR: techniques for mitigating bandwidth bloat in gigascale DRAM caches., , and . ISCA, page 198-210. ACM, (2015)IDYLL: Enhancing Page Translation in Multi-GPUs via Light Weight PTE Invalidations., , , , , and . MICRO, page 1163-1177. ACM, (2023)HMG: Extending Cache Coherence Protocols Across Modern Hierarchical Multi-GPU Systems., , , , , and . HPCA, page 582-595. IEEE, (2020)Automatic SMT threading for OpenMP applications on the Intel Xeon Phi co-processor., , , , , and . ROSS@ICS, page 7:1-7:7. ACM, (2014)Improving the Precise Interrupt Mechanism of Software-Managed TLB Miss Handlers., and . HiPC, volume 2228 of Lecture Notes in Computer Science, page 282-293. Springer, (2001)