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Gate Sizing for Power-Delay Optimization at Transistor-level Monolithic 3D-Integrated Circuits., , and . LASCAS, page 1-4. IEEE, (2020)A 915 MHz UHF low power RFID tag., , , , , , , and . SBCCI, page 276-281. ACM, (2007)Timing-aware ATPG for critical paths with multiple TSVs., , , , , and . DDECS, page 116-121. IEEE Computer Society, (2014)TSV aware timing analysis and diagnosis in paths with multiple TSVs., , , , , and . VTS, page 1-6. IEEE Computer Society, (2014)A Flexible Design Flow for a Low Power RFID Tag., , , , , , , and . VLSI-SoC, page 300-303. IEEE, (2007)Computing detection probability of delay defects in signal line tsvs., , , , , , , and . ETS, page 1-6. IEEE Computer Society, (2013)Clip Clustering for Early Lithographic Hotspot Classification., , , and . LASCAS, page 149-152. IEEE, (2019)A Passive 915 MHz UHF RFID Tag., , , , , , , and . ISQED, page 348-351. IEEE Computer Society, (2008)Through-Silicon-Via resistive-open defect analysis., , , , , and . ETS, page 1. IEEE Computer Society, (2012)