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Design-Time Railway Capacity Verification using SAT modulo Discrete Event Simulation., , and . FMCAD, page 1-9. IEEE, (2018)Testing Cyber-Physical Systems Using a Line-Search Falsification Method., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (8): 2393-2406 (2022)Splittable pseudorandom number generators using cryptographic hashing., and . Haskell, page 47-58. ACM, (2013)QuickerCheck: Implementing and Evaluating a Parallel Run-Time for QuickCheck., , , and . CoRR, (2024)Specification Based Testing with QuickCheck, and . The Fun of Programming, Cornerstones of Computing, Palgrave, Houndmills, England, (2003)The Verse Calculus: A Core Calculus for Deterministic Functional Logic Programming., , , , , , , and . Proc. ACM Program. Lang., 7 (ICFP): 417-447 (August 2023)Towards secure IoT programming in Haskell., , , and . Haskell@ICFP, page 136-150. ACM, (2020)Automated Drawing of Railway Schematics Using Numerical Optimization in SAT., , and . IFM, volume 11918 of Lecture Notes in Computer Science, page 341-359. Springer, (2019)Testing Safety PLCs Using QuickCheck., , , , and . CASE, page 1-6. IEEE, (2019)QuickerCheck: Implementing and Evaluating a Parallel Run-Time for QuickCheck., , , and . IFL, page 9:1-9:12. ACM, (2023)