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Way Stealing: A Unified Data Cache and Architecturally Visible Storage for Instruction Set Extensions.

, , , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (1): 62-75 (2014)

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Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions., , , , and . HiPEAC, volume 5952 of Lecture Notes in Computer Science, page 126-140. Springer, (2010)A 128×128 Single-Photon Imager with on-Chip Column-Level 10b Time-to-Digital Converter Array Capable of 97ps Resolution., , , , and . ISSCC, page 44-45. IEEE, (2008)Speculative DMA for architecturally visible storage in instruction set extensions., , , and . CODES+ISSS, page 243-248. ACM, (2008)Way Stealing: cache-assisted automatic instruction set extensions., , , and . DAC, page 31-36. ACM, (2009)A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions., , , , , , , and . CHES, volume 5747 of Lecture Notes in Computer Science, page 205-219. Springer, (2009)Single-photon synchronous detection., , , , and . ESSCIRC, page 114-117. IEEE, (2008)Optically-Clocked Instruction Set Extensions for High Efficiency Embedded Processors., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 59-I (3): 604-615 (2012)MPSoC Design Using Application-Specific Architecturally Visible Communication., , , and . HiPEAC, volume 5409 of Lecture Notes in Computer Science, page 183-197. Springer, (2009)Way Stealing: A Unified Data Cache and Architecturally Visible Storage for Instruction Set Extensions., , , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (1): 62-75 (2014)Virtual Ways: Low-Cost Coherence for Instruction Set Extensions with Architecturally Visible Storage., , , , and . ACM Trans. Archit. Code Optim., 11 (2): 15:1-15:26 (2014)