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Disambiguation of "Asavoae, Mihail"

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Work in Progress: Automatic Construction of Pipeline Datapaths from High-Level HDL Code.

, , , and . RTAS, page 305-308. IEEE, (2022)

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Mihail Niculescu

Mihail Lungu

Mihail Cosoiu

Mihail Musceleanu

Mihail Petrov

 

Other publications of authors with the same name

Fault-Resistant Partitioning of Secure CPUs for System Co-Verification against Faults., , , , , , , , and . IACR Cryptol. ePrint Arch., (2024)Work in Progress: Automatic Construction of Pipeline Datapaths from High-Level HDL Code., , , and . RTAS, page 305-308. IEEE, (2022)Towards Formal Co-validation of Hardware and Software Timing Models of CPSs., , , , and . CyPhy/WESE, volume 11971 of Lecture Notes in Computer Science, page 203-227. Springer, (2019)μARCHIFI: Formal Modeling and Verification Strategies for Microarchitectural Fault Injections., , , , and . FMCAD, page 101-109. IEEE, (2023)Deriving Pipeline Models for Timing Analysis from High-Level HDL Processor Designs., , , and . MEMOCODE, page 1-8. IEEE, (2022)Context-Updates Analysis and Refinement in Chisel., , and . SPIN, volume 10869 of Lecture Notes in Computer Science, page 328-346. Springer, (2018)Exploration of Fault Effects on Formal RISC-V Microarchitecture Models., , , , and . FDTC, page 73-83. IEEE, (2022)From the Standards to Silicon: Formally Proved Memory Controllers., , and . NFM, volume 13903 of Lecture Notes in Computer Science, page 295-311. Springer, (2023)On Abstractions for Timing Analysis in the $K$ Framework., , and . FOPARA, volume 7177 of Lecture Notes in Computer Science, page 90-107. Springer, (2011)Memory Policy Analysis for Semantics Specifications in Maude., , and . LOPSTR, volume 9527 of Lecture Notes in Computer Science, page 293-310. Springer, (2015)