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Vertically-addressed test structures (VATS) for 3D IC variability and stress measurements., , and . ISQED, page 96-103. IEEE, (2013)HaDeS: architectural synthesis for <u>h</u>eterogeneous <u>d</u>ark <u>s</u>ilicon chip multi-processors., , , and . DAC, page 173:1-173:7. ACM, (2013)Thundervolt: enabling aggressive voltage underscaling and timing error resilience for energy efficient deep learning accelerators., , , and . DAC, page 19:1-19:6. ACM, (2018)Low cost permanent fault detection using ultra-reduced instruction set co-processors., , and . DATE, page 933-938. EDA Consortium San Jose, CA, USA / ACM DL, (2013)BandiTS: Dynamic timing speculation using multi-armed bandit based optimization., and . DATE, page 922-925. IEEE, (2017)EmPower: FPGA based rapid prototyping of dynamic power management algorithms for multi-processor systems on chip., , , and . FPL, page 41-48. IEEE, (2012)Fragility of the Commons under Prospect-Theoretic Risk Attitudes., , and . CoRR, (2014)A Feature-Based On-Line Detector to Remove Adversarial-Backdoors by Iterative Demarcation., , , , and . IEEE Access, (2022)Lost at C: A User Study on the Security Implications of Large Language Model Code Assistants., , , , , and . USENIX Security Symposium, page 2205-2222. USENIX Association, (2023)Characterizing and Optimizing End-to-End Systems for Private Inference., , , , and . CoRR, (2022)