Author of the publication

Enabling Ultra-Low Power Ultrasound Imaging with Compute-in-Memory Sparse Reconstruction Accelerator.

, , , , , and . BioCAS, page 1-5. IEEE, (2023)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A 1.11 mm2 Guidewire IVUS SoC with ±50°-Range Plane Wave Transmit Beamforming., , , , , and . ESSCIRC, page 309-312. IEEE, (2023)Design of Non-volatile Capacitive Crossbar Array for In-Memory Computing., , , , and . IMW, page 1-4. IEEE, (2021)A 0.029MM2 17-FJ/Conv.-Step CT $\Delta\Sigma$ ADC with 2nd-Order Noise-Shaping SAR Quantizer., , , , and . VLSI Circuits, page 201-202. IEEE, (2018)Error-Feedback Mismatch Error Shaping for High-Resolution Data Converters., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (4): 1342-1354 (2019)A Scaling Compatible, Synthesis Friendly VCO-based Delta-sigma ADC Design and Synthesis Methodology., , , and . DAC, page 12:1-12:6. ACM, (2017)An 82dB-SNDR Input-Driving-Relaxed Noise-Shaping SAR with Amplifier-Reused In-Loop Buffering and NTF Leakage Reshaping., , , , , , and . CICC, page 1-2. IEEE, (2024)Low-power Scaling-friendly Ring Oscillator based ΔΣ ADC., , and . ISCAS, page 1-5. IEEE, (2018)Hierarchical and Analytical Placement Techniques for High-Performance Analog Circuits., , , , and . ISPD, page 55-62. ACM, (2017)Enabling Ultra-Low Power Ultrasound Imaging with Compute-in-Memory Sparse Reconstruction Accelerator., , , , , and . BioCAS, page 1-5. IEEE, (2023)A 0.01mm2 25µW 2MS/s 74dB-SNDR Continuous-Time Pipelined-SAR ADC with 120fF Input Capacitor., , , , , , , , and . ISSCC, page 64-66. IEEE, (2019)