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Disambiguation of "Galy, Philippe"

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Fast Measurement of BTI on 28nm Fully Depleted Silicon-On-Insulator MOSFETs at Cryogenic Temperature down to 4K.

, , , , , , , , , and . IRPS, page 7. IEEE, (2022)

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Bernd Galyga

Henri Galy

Islam Galy Khalil

Philippe Dreuw

Philippe Kersting

 

Other publications of authors with the same name

Experimental measurements and 3D simulation of the parasitic lateral bipolar transistor triggering within a single finger gg-nMOS under ESD., , , , and . Microelectron. Reliab., 44 (9-11): 1775-1780 (2004)Experimental and 3D simulation correlation of a gg-nMOS transistor under high current pulse., , , , , , and . Microelectron. Reliab., 42 (9-11): 1299-1302 (2002)Circuit optimization of 4T, 6T, 8T, 10T SRAM bitcells in 28nm UTBB FD-SOI technology using back-gate bias control., , , , , and . ESSCIRC, page 415-418. IEEE, (2013)Temperature and Gate Leakage Influence on the Z2-FET Memory Operation., , , , , , and . ESSDERC, page 238-241. IEEE, (2019)Preliminary results on TFET - Gated diode in thin silicon film for IO design & ESD protection in 28nm UTBB FD-SOI CMOS technology., and . ICICDT, page 1-4. IEEE, (2016)7-mm low-latency inter-chiplet serial link with silicon interposer., , , , and . MWSCAS, page 683-686. IEEE, (2020)6T SRAM performance and power gain using double gate MOS in 28nm FDSOI technology., , , , and . ICICDT, page 89-92. IEEE, (2013)Toward Gated-Diode-BIMOS for thin silicon ESD protection in advanced FD-SOI CMOS technologies., , , , and . ICICDT, page 1-4. IEEE, (2017)Optimized in situ heating control on a new MOS device structure in 28nm UTBB FD-SOI CMOS technology., , and . ICICDT, page 157-160. IEEE, (2018)Computation of Self-Induced Magnetic Field Effects Including the Lorentz Force for Fast-Transient Phenomena in Integrated-Circuit Devices., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 33 (6): 893-902 (2014)