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Disambiguation of "Nomura, Kumiko"

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D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory.

, , , , , , , , and . DATE, page 1813-1818. EDA Consortium San Jose, CA, USA / ACM DL, (2013)

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Toru Nomura

Kumiko Nakagawa

Yutaka Nomura

Kumiko Gnibba

Teiji Nomura

 

Other publications of authors with the same name

D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory., , , , , , , , and . DATE, page 1813-1818. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Optimal adaptive parallel diagnosis for arrays., , and . ISCAS (3), page 854-857. IEEE, (2003)Perspectives and Issues in 3D-IC from Designers' Point of View., , , , and . ISCAS, page 73-76. IEEE, (2009)Novel nonvolatile memory hierarchies to realize "normally-off mobile processors"., , , , and . ASP-DAC, page 6-11. IEEE, (2014)Nonlinear Operation of Static-Binary Neuron Circuits and Dynamic Memristive Devices for STDP Learning., , , , , , , , and . ISCAS, page 1-5. IEEE, (2019)Performance analysis of 3D-IC for multi-core processors in sub-65nm CMOS technologies., , , , and . ISCAS, page 2876-2879. IEEE, (2010)On the two-dimensional orthogonal drawing of series-parallel graphs., , and . ISCAS, IEEE, (2006)Novel STT-MRAM-based last level caches for high performance processors using normally-off architectures., , , , , and . ISIC, page 316-319. IEEE, (2014)Proposal, analysis and demonstration of Analog/Digital-mixed Neural Networks based on memristive device arrays., , , , and . ISCAS, page 1-5. IEEE, (2018)On the two-dimensional orthogonal drawing of series-parallel graphs., , and . Discret. Appl. Math., 157 (8): 1885-1895 (2009)