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Width minimization in the Single-Electron Transistor array synthesis.

, , , , , , and . DATE, page 1-4. European Design and Automation Association, (2014)

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Video analytics using beyond CMOS devices., , , , , and . DATE, page 1-5. European Design and Automation Association, (2014)Green transistors to green architectures., and . ISLPED, page 429-430. ACM, (2009)Opportunties and challenges of tunnel FETs., , and . ISCAS, page 397-400. IEEE, (2016)Investigation of electrically gate-all-around hexagonal nanowire FET (HexFET) architecture for 5 nm node logic and SRAM applications., , , , , , and . ESSDERC, page 188-191. IEEE, (2017)Power and Area Efficient FPGA Building Blocks Based on Ferroelectric FETs., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (5): 1780-1793 (2019)A Hybrid FeMFET-CMOS Analog Synapse Circuit for Neural Network Training and Inference., , , , , and . ISCAS, page 1-5. IEEE, (2020)A FeFET Based Processing-In-Memory Architecture for Solving Distributed Least-Square Optimizations., , , , , , , , , and 2 other author(s). DRC, page 1-2. IEEE, (2018)Steep switching tunnel FET: A promise to extend the energy efficient roadmap for post-CMOS digital and analog/RF applications., , and . ISLPED, page 145-150. IEEE, (2013)Improving energy efficiency of multi-threaded applications using heterogeneous CMOS-TFET multicores., , , , , and . ISLPED, page 247-252. IEEE/ACM, (2011)Connecting spectral techniques for graph coloring and eigen properties of coupled dynamics: A pathway for solving combinatorial optimizations (Invited paper)., , , , and . ICCAD, page 800-804. IEEE, (2017)