( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
Explicit Expression and Simultaneous Optimization of Placement and Routing for Analog IC Layouts.

, , , и . ASP-DAC/VLSI Design, стр. 467-472. IEEE Computer Society, (2002)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

No persons found for author name Nakatake, Shigetoshi
add a person with the name Nakatake, Shigetoshi
 

Другие публикации лиц с тем же именем

Layout-aware variation evaluation of analog circuits and its validity on op-amp designs., , , , , и . ACM Great Lakes Symposium on VLSI, стр. 247-252. ACM, (2011)Post-placement STI well width adjusting by geometric programming for device mobility enhancement in critical path., , , и . ISCAS, стр. 929-932. IEEE, (2010)Consistent floorplanning with super hierarchical constraints., , и . ISPD, стр. 144-149. ACM, (2001)Abstraction and optimization of consistent floorplanning with pillar block constraints., , , и . ASP-DAC, стр. 19-24. IEEE Computer Society, (2004)Sequence-Pair Based Compaction under Equi-Length Constraint., , , и . APCCAS, стр. 1015-1018. IEEE, (2006)Low-Power and Low-Variability Programmable Delay Element and Its Application to Post-Silicon Skew Tuning., , , и . ISVLSI, стр. 167-171. IEEE Computer Society, (2015)A retargeting methodology of nano-watt CMOS reference circuit based on advanced compact MOSFET model., , , , и . ISCAS, стр. 938-941. IEEE, (2012)The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications., , , и . ICCAD, стр. 418-425. ACM / IEEE Computer Society, (1998)On-chip resistance configuration by subthreshold MOSFET-array for ultra weak current sensing., и . APCCAS, стр. 261-264. IEEE, (2019)A Perceptron Circuit with DAC-Based Multiplier for Sensor Analog Front-Ends., , , и . NGCAS, стр. 93-96. IEEE, (2017)