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A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based FPGAs.

E. Reddy, V. Chandrasekhar, M. Sashikánth, V. Kamakoti, and V. Narayanan. FPT, page 121-128. IEEE, (2004)

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Vikram Mehta

Chandrasekhar Boyapati

Chandrasekhar Iyer

Chandrasekhar Vavilala

Vikram Menon

Other publications of authors with the same name

Uplink Capacity and Interference Avoidance for Two-Tier Cellular Networks.V. Chandrasekhar, and J. Andrews. GLOBECOM, page 3322-3326. IEEE, (2007)Coverage in multi-antenna two-tier networks.V. Chandrasekhar, M. Kountouris, and J. Andrews. IEEE Trans. Wirel. Commun., 8 (10): 5314-5327 (2009)A function generator-based reconfigurable system.V. Garg, V. Chandrasekhar, M. Sashikánth, and V. Kamakoti. ASP-DAC, page 905-909. ACM Press, (2005)Detecting SEU-Caused Routing Errors in SRAM-Based FPGAs.E. Reddy, V. Chandrasekhar, M. Sashikánth, V. Kamakoti, and N. Vijaykrishnan. VLSI Design, page 736-741. IEEE Computer Society, (2005)Online Detection and Diagnosis of Multiple Configuration Upsets in LUTs of SRAM-Based FPGAs.E. Reddy, V. Chandrasekhar, M. Sashikánth, V. Kamakoti, and N. Vijaykrishnan. IPDPS, IEEE Computer Society, (2005)Femtocell Access Control in the TDMA/OFDMA Uplink.P. Xia, V. Chandrasekhar, and J. Andrews. GLOBECOM, page 1-5. IEEE, (2010)From homogeneous to heterogeneous networks: A 3GPP Long Term Evolution rel 8/9 case study.R. Bendlin, V. Chandrasekhar, R. Chen, A. Ekpenyong, and E. Onggosanusi. CISS, page 1-5. IEEE, (2011)Coverage in Tiered Cellular Networks with Spatial Diversity.V. Chandrasekhar, M. Kountouris, and J. Andrews. GLOBECOM, page 1-6. IEEE, (2009)Optimal power allocation for sum capacity of a slotted three-cell system.V. Chandrasekhar, Z. Shen, and V. Sundararajan. ICASSP, page 3161-3164. IEEE, (2008)A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based FPGAs.E. Reddy, V. Chandrasekhar, M. Sashikánth, V. Kamakoti, and V. Narayanan. FPT, page 121-128. IEEE, (2004)

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Disambiguation of "Chandrasekhar, Vikram"

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A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based FPGAs.

Please choose a person to relate this publication to

Vikram Mehta

Chandrasekhar Boyapati

Chandrasekhar Iyer

Chandrasekhar Vavilala

Vikram Menon

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Chandrasekhar, Vikram"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based FPGAs.

Please choose a person to relate this publication to

Vikram Mehta

Chandrasekhar Boyapati

Chandrasekhar Iyer

Chandrasekhar Vavilala

Vikram Menon

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based FPGAs.