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A 2×2-16×16 Reconfigurable GGMD Processor for MIMO Communication Systems.

, , , and . ISCAS, page 1-5. IEEE, (2018)

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Power and area reduction in multi-stage addition using operand segmentation., , , and . VLSI-DAT, page 1-4. IEEE, (2013)A Systolic Array Based GTD Processor With a Parallel Algorithm., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (4): 1099-1108 (2015)Iterative Receiver with a Lattice-Reduction-Aided MIMO Detector for IEEE 802.11ax., , , , , and . GLOBECOM, page 1-6. IEEE, (2020)Design optimization for ADMM-Based SVM Training Processor for Edge Computing., , and . AICAS, page 1-5. IEEE, (2021)4.7 A 91mW 90fps Super-Resolution Processor for Full HD Images., , , and . ISSCC, page 66-68. IEEE, (2021)A 96.2nJ/class Neural Signal Processor with Adaptable Intelligence for Seizure Prediction., , and . ISSCC, page 1-3. IEEE, (2022)24.5 A 0.5V 1.27mW nose-on-a-chip for rapid diagnosis of ventilator-associated pneumonia., , , , , , , , , and 9 other author(s). ISSCC, page 420-421. IEEE, (2014)Hardware-efficient EVD processor architecture in FastICA for epileptic seizure detection., , , and . APSIPA, page 1-4. IEEE, (2012)A 1.96 Gb/s Massive MU-MIMO Detector for Next-Generation Cellular Systems., , , , and . VLSI Circuits, page 1-2. IEEE, (2020)Design of a 0.5 V 1.68mW nose-on-a-chip for rapid screen of chronic obstructive pulmonary disease., , , , , , , , , and 1 other author(s). BioCAS, page 592-595. IEEE, (2016)