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Fast dynamic simulation of VLSI circuits using reduced order compact macromodel of standard cells., , , and . BMAS, page 75-80. IEEE, (2010)Hetero2 3D integration: A scheme for optimizing efficiency/cost of Chip Multiprocessors., , , , , , and . ISQED, page 1-7. IEEE, (2013)Coordinating 3D designs: Interface IP, standards or free form?, , , , , , and . 3DIC, page 1-3. IEEE, (2011)Catena: A 0.5-V Sub-0.4-mW 16-Core Spatial Array Accelerator for Mobile and Embedded Computing., , , , , and . VLSI Circuits, page 54-. IEEE, (2019)Junction-Level Thermal Analysis of 3-D Integrated Circuits Using High Definition Power Blurring., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 31 (5): 676-689 (2012)Pathfinder3D: A framework for exploring early thermal tradeoffs in 3DIC., , and . ICICDT, page 1-6. IEEE, (2014)SPICE-compatible physical model of nanocrystal floating gate devices for circuit simulation., , , , and . IET Circuits Devices Syst., 5 (6): 477-483 (2011)Pathfinder 3D: A flow for system-level design space exploration., , , , , , and . 3DIC, page 1-8. IEEE, (2011)Exploring early design tradeoffs in 3DIC., , , , and . ISCAS, page 545-549. IEEE, (2013)