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Disambiguation of "Devos, Harald"

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FPGA Design Methodology for a Wavelet-Based Scalable Video Decoder.

, , , , and . SAMOS, volume 4599 of Lecture Notes in Computer Science, page 169-178. Springer, (2007)

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Bianca Devos

Helmut Devos

Laetitia Devos

Margareta Anna Victor Devos

Harald Bertram

Moderne kathetergesteuerte Diagnostik und Therapie kongenitaler kardiovaskulärer Anomalien. MedH Hannover, habilitation, (2009)
 

Other publications of authors with the same name

Energy Scalability and the RESUME Scalable Video Codec., , , and . Power-aware Computing Systems, volume 07041 of Dagstuhl Seminar Proceedings, Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI), Schloss Dagstuhl, Germany, (2007)Optimizing the FPGA Memory Design for a Sobel Edge Detector., , and . ERSA, page 299-300. CSREA Press, (2009)A Parallel for Loop Memory Template for a High Level Synthesis Compiler., , , and . DSD, page 449-455. IEEE Computer Society, (2010)Embedding Smart Buffers for Window Operations in a Stream-Oriented C-to-VHDL Compiler., , , and . DELTA, page 142-147. IEEE Computer Society, (2008)Finding and Applying Loop Transformations for Generating Optimized FPGA Implementations., , , , , and . Trans. High Perform. Embed. Archit. Compil., (2007)Automatic tool flow for shift-register-LUT reconfiguration: making run-time reconfiguration fast and easy (abstract only)., , , and . FPGA, page 287. ACM, (2010)A Hardware-Friendly Wavelet Entropy Codec for Scalable Video., , , , and . DATE, page 14-19. IEEE Computer Society, (2005)FPGA Design Methodology for a Wavelet-Based Scalable Video Decoder., , , , and . SAMOS, volume 4599 of Lecture Notes in Computer Science, page 169-178. Springer, (2007)07041 Working Group - Towards Interfaces for Integrated Performance and Power Analysis and Simulation., , , , , , , , , and 1 other author(s). Power-aware Computing Systems, volume 07041 of Dagstuhl Seminar Proceedings, Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI), Schloss Dagstuhl, Germany, (2007)Loop Transformations for the Optimized Generation of Reconfigurable Hardware.. Ghent University, Belgium, (2008)base-search.net (ftunivgent:oai:archive.ugent.be:469156).