( en | de | ru )

 

Disambiguation of "Sciuto, Donatella"

Author of the publication

copydeleteadd this publication to your clipboard
TaBit: A framework for task graph to bitstream generation.

, , , , , and . ICSAMOS, page 201-208. IEEE, (2012)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Donatella Cesare

Donatella Cesare

Donatella Giovannini

Donatella Germanese

Donatella Fiala

 

Other publications of authors with the same name

Optimization techniques for multiple output function synthesis., , and . EURO-DAC, page 545-551. EEE Computer Society, (1991)GECO: A Tool for Automatic Generation of Error Control Codes for Computer Applications., , and . ISCAS, page 912-915. IEEE, (1995)Data Path Testability Analysis Based on BDDs., , and . ISCAS, page 2012-2014. IEEE, (1995)Two-Dimensional Sequential Array Architectures: Design for Testability Approaches., , and . ISCAS, page 81-84. IEEE, (1994)An Output/State Encoding for Self-Checking Finite State Machine., and . ISCAS, page 2136-2139. IEEE, (1995)Using Critical Success Factors for Assessing Critical Activities in ERP Implementation within SMEs., , and . ICEIS (1), page 285-292. (2005)Task Partitioning for the Scheduling on Reconfigurable Systems driven by Specification Self-Similarity., , , и . ERSA, стр. 78-84. CSREA Press, (2007)The Impact of Source Code Transformations on Software Power and Energy Consumption., , , и . Journal of Circuits, Systems, and Computers, 11 (5): 477-502 (2002)Ant colony optimization for mapping and scheduling in heterogeneous multiprocessor systems., , , , и . ICSAMOS, стр. 142-149. IEEE, (2008)An Application Mapping Methodology and Case Study for Multi-Processor On-Chip Architectures., , , , и . VLSI-SoC, стр. 146-151. IEEE, (2006)