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Calculating frequency-dependent inductance of VLSI interconnect by complete multiple reciprocity boundary element method.

, , and . ASP-DAC, page 844-849. IEEE, (2006)

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Calculating frequency-dependent inductance of VLSI interconnect by complete multiple reciprocity boundary element method., , and . ASP-DAC, page 844-849. IEEE, (2006)BBGP-sDFO: Batch Bayesian and Gaussian Process Enhanced Subspace Derivative Free Optimization for High-Dimensional Analog Circuit Synthesis., , , , , , , , , and 3 other author(s). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 43 (2): 417-430 (February 2024)A Batched Bayesian Optimization Approach for Analog Circuit Synthesis via Multi-Fidelity Modeling., , , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (2): 347-359 (February 2023)Efficient Approximation Algorithms for Chemical Mechanical Polishing Dummy Fill., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 30 (3): 402-415 (2011)A Batch Bayesian Optimization Approach For Analog Circuit Synthesis Based On Multi-Points Selection Criterion., , , , , and . ISCAS, page 2886-2890. IEEE, (2022)Efficient High-Level Synthesis of Approximate Computing Circuits via Multi-fidelity Modeling., , , and . ASICON, page 1-4. IEEE, (2021)LinEasyBO: Scalable Bayesian Optimization Approach for Analog Circuit Synthesis via One-Dimensional Subspaces., , , , and . MLCAD, page 27-34. ACM / IEEE, (2022)An Efficient Non-Gaussian Sampling Method for High Sigma SRAM Yield Analysis., , , , , and . ACM Trans. Design Autom. Electr. Syst., 23 (3): 36:1-36:23 (2018)An Efficient Batch Constrained Bayesian Optimization Approach for Analog Circuit Synthesis via Multi-objective Acquisition Ensemble., , , , and . CoRR, (2021)Bayesian Optimization Approach for Analog Circuit Synthesis Using Neural Network., , , , , and . DATE, page 1463-1468. IEEE, (2019)