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Small delay testing for TSVs in 3-D ICs., , , , , , and . DAC, page 1031-1036. ACM, (2012)Enabling inter-die co-optimization in 3-D IC with TSVs., , , , and . VLSI-DAT, page 1-4. IEEE, (2013)A SAR ADC missing-decision level detection and removal technique., , , and . VTS, page 31-36. IEEE Computer Society, (2012)Time-to-Digital Converter Compiler for On-Chip Instrumentation., , , and . IEEE Des. Test, 37 (4): 101-107 (2020)A built-in self-test scheme for 3D RAMs., , , , , , and . ITC, page 1-9. IEEE Computer Society, (2012)Temperature-aware online testing of power-delivery TSVs., , , and . 3DIC, page TS10.3.1-TS10.3.6. IEEE, (2015)Performance Characterization of TSV in 3D IC via Sensitivity Analysis., , , , and . Asian Test Symposium, page 389-394. IEEE Computer Society, (2010)etection of SRAM cell stability by lowering array supply voltage., , , , and . Asian Test Symposium, page 268-273. IEEE Computer Society, (2000)A built-in self-test scheme for the post-bond test of TSVs in 3D ICs., , , , , and . VTS, page 20-25. IEEE Computer Society, (2011)An FPGA-based test platform for analyzing data retention time distribution of DRAMs., , , , , and . VLSI-DAT, page 1-4. IEEE, (2013)