( en | de | ru )

 

Disambiguation of "Bruguera, Javier D."

Author of the publication

copydeleteadd this publication to your clipboard
A Digit-by-Digit Algorithm for mth Root Extraction.

, , , and . IEEE Trans. Computers, 56 (12): 1696-1706 (2007)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Javier Dreyer

Javier Manero

Javier Jáurequi

Javier Papa

Javier Arpón

 

Other publications of authors with the same name

High-Throughput Architecture for H.264/AVC CABAC Compression System., and . IEEE Trans. Circuits Syst. Video Techn., 16 (11): 1376-1384 (2006)Floating-Point Multiply-Add-Fused with Reduced Latency., and . IEEE Trans. Computers, 53 (8): 988-1003 (2004)On-line high-radix exponential with selection by rounding., , and . ISCAS (4), page 121-124. IEEE, (2003)Cordic based parallel/pipelined architecture for the Hough transform., , , , and . VLSI Signal Processing, 12 (3): 207-221 (1996)Radix-64 Floating-Point Division and Square Root: Iterative and Pipelined Units.. IEEE Trans. Computers, 72 (10): 2990-3001 (October 2023)Gaussian elimination with pivoting on hypercubes., , , , and . Parallel Comput., 14 (1): 51-60 (1990)A New Architecture for fast Arithmetic Coding in H.264 Advanced Video Coder., and . DSD, page 298-305. IEEE Computer Society, (2005)Analysis of the Impact of Different Methods for Division/Square Root Computation in the Performance of a Superscalar Microprocessor., , and . DSD, page 218-225. IEEE Computer Society, (2002)Concentric Strips: Algorithms and Architecture for the Compression/Decompression of Triangle Meshes., , , and . 3DPVT, page 380-383. IEEE Computer Society, (2002)Arithmetic Image Coding/Decoding Architecture Based on a Cache Memory., , and . EUROMICRO, page 10139-. IEEE Computer Society, (1998)