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Power-Efficient Mapping of Large Applications on Modern Heterogeneous FPGAs.

, , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (12): 2508-2521 (2021)

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Design Abstraction for Autonomous Adaptive Hardware Systems on FPGAs.. AHS, page 142-147. IEEE, (2018)Automated Partial Reconfiguration Design for Adaptive Systems with CoPR for Zynq., and . FCCM, page 202-205. IEEE Computer Society, (2014)Efficient Overlay Architecture Based on DSP Blocks., , and . FCCM, page 25-28. IEEE Computer Society, (2015)Experiments in Mapping Expressions to DSP Blocks., and . FCCM, page 101. IEEE Computer Society, (2014)DeCO: A DSP Block Based FPGA Accelerator Overlay with Low Overhead Interconnect., , , , and . FCCM, page 1-8. IEEE Computer Society, (2016)Novel FPGA-Based Implementation of Median and Weighted Median Filters for Image Processing., , and . FPL, page 142-147. IEEE, (2005)Streaming Overlay Architecture for Lightweight LSTM Computation on FPGA SoCs., and . ACM Trans. Reconfigurable Technol. Syst., 16 (1): 8:1-8:26 (March 2023)Power-Efficient Mapping of Large Applications on Modern Heterogeneous FPGAs., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (12): 2508-2521 (2021)FPGA Dynamic and Partial Reconfiguration: A Survey of Architectures, Methods, and Applications., and . ACM Comput. Surv., 51 (4): 72:1-72:39 (2018)Runtime Abstraction for Autonomous Adaptive Systems on Reconfigurable Hardware., and . DATE, page 1616-1621. IEEE, (2021)