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High-throughput Hardware Architectures of the JH Round-three SHA-3 Candidate - An FPGA Design and Implementation Approach., , , , , and . SECRYPT, page 126-135. SciTePress, (2012)Implementation of HSSec: a high-speed cryptographic co-processor., , , and . ETFA, page 625-631. IEEE, (2007)Spectra using data distribution and covariance modelling., , and . ICASSP, page 642-645. IEEE, (1984)A VLSI synthesis tool for complementary output delta modulation FIR filters., , , and . Microprocess. Microprogramming, 34 (1-5): 139-142 (1992)A low power fault secure timer implementation based on the Gray encoding scheme., , , and . ICECS, page 537-540. IEEE, (2002)Fault secure binary counter design., , and . ICECS, page 1659-1662. IEEE, (1999)System-level power optimizing data-flow transformations for multimedia applications realized on programmable multimedia processors., , , and . ICECS, page 1733-1736. IEEE, (1999)A Compiler Method for Memory-Conscious Mapping of Applications on Coarse-Grained Reconfigurable Architectures., , and . IPDPS, IEEE Computer Society, (2005)Performance Improvements in Microprocessor Systems Utilizing a Copressor Data-Path., , and . ICSAMOS, page 85-92. IEEE, (2006)Ultra High Speed SHA-256 Hashing Cryptographic Module for IPSec Hardware/Software Codesign., , , , , and . SECRYPT, page 309-313. SciTePress, (2010)