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A hybrid and adaptive model for predicting register file and SRAM power using a reference design., , and . DAC, page 62-67. ACM, (2012)A System Verilog Rewriting System for RTL Abstraction with Pentium Case Study., , , , and . MEMOCODE, page 79-88. IEEE Computer Society, (2008)Statistical quality modeling of approximate hardware., , , , , and . ISQED, page 163-168. IEEE, (2016)HALWPE: Hardware-Assisted Light Weight Performance Estimation for GPUs., , , and . DAC, page 80:1-80:6. ACM, (2017)Power and CAD considerations for the 1.75mbyte, 1.2ghz L2 cache on the alpha 21364 CPU., , , , , , , , , and 7 other author(s). ACM Great Lakes Symposium on VLSI, page 1-6. ACM, (2002)Cross-FPGA Power Estimation from High Level Synthesis via Transfer-Learning., , , and . FPGA, page 187. ACM, (2024)P4: Phase-based power/performance prediction of heterogeneous systems via neural networks., , , , and . ICCAD, page 683-690. IEEE, (2017)SimTrace: Capturing over Time Program Phase Behavior., , , , and . ISPASS, page 226-228. IEEE, (2020)MQL: ML-Assisted Queuing Latency Analysis for Data Center Networks., , , , , , and . ISPASS, page 50-60. IEEE, (2023)Application Performance Prediction and Optimization Under Cache Allocation Technology., , , and . DATE, page 1285-1288. IEEE, (2019)