Author of the publication

Profile-guided microarchitectural floor planning for deep submicron processor design.

, , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (7): 1289-1300 (2006)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

3D module placement for congestion and power noise reduction., , and . ACM Great Lakes Symposium on VLSI, page 458-461. ACM, (2005)Reliability-aware floorplanning for 3D circuits., , and . SoCC, page 81-82. IEEE, (2005)Profile-guided microarchitectural floor planning for deep submicron processor design., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (7): 1289-1300 (2006)Optical routing for 3D system-on-package., , and . DATE, page 337-338. European Design and Automation Association, Leuven, Belgium, (2006)Layer assignment for reliable system-on-package., and . ASP-DAC, page 31-37. IEEE Computer Society, (2004)Profile-guided microarchitectural floorplanning for deep submicron processor design., , , , and . DAC, page 634-639. ACM, (2004)Net and Pin Distribution for 3D Package Global Routing., , and . DATE, page 1410-1411. IEEE Computer Society, (2004)Decoupling capacitor planning and sizing for noise and leakage reduction., , and . ICCAD, page 395-400. ACM, (2006)