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Disambiguation of "Pan, David Z."

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Cross-Lock: Dense Layout-Level Interconnect Locking using Cross-bar Architectures.

, , , and . ACM Great Lakes Symposium on VLSI, page 147-152. ACM, (2018)

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David Tse-chien Pan

Z Taufig

Xiaoqing Pan

Petra Pan

Pan Li

 

Other publications of authors with the same name

Skew Bounded Buffer Tree Resynthesis For Clock Power Optimization., , , , , and . ACM Great Lakes Symposium on VLSI, page 87-90. ACM, (2015)Total power optimization combining placement, sizing and multi-Vt through slack distribution management., , and . ASP-DAC, page 352-357. IEEE, (2008)BOB-router: A new buffering-aware global router with over-the-block routing resources optimization., , and . ASP-DAC, page 513-518. IEEE, (2014)Self-aligned double patterning layout decomposition with complementary e-beam lithography., , and . ASP-DAC, page 143-148. IEEE, (2014)Machine learning and pattern matching in physical design., , , and . ASP-DAC, page 286-293. IEEE, (2015)A high-performance triple patterning layout decomposer with balanced density., , , , , and . ICCAD, page 163-169. IEEE, (2013)Machine learning for IC design and technology co-optimization in extreme scaling.. VLSI-DAT, page 1. IEEE, (2018)Editorial: ACM Transactions on Design Automation of Electronics Systems and Beyond., , and . ACM Trans. Design Autom. Electr. Syst., 20 (1): 1:1-1:2 (2014)ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction., , , and . DAC, page 504-509. ACM, (2008)AENEID: a generic lithography-friendly detailed router based on post-RET data learning and hotspot detection., , , and . DAC, page 795-800. ACM, (2011)