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An approach to the design of low-jitter differential clock recovery circuits for high performance ADCs.

, , , и . LASCAS, стр. 1-4. IEEE, (2015)

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Eduardo Monari

Eduardo Maurô

Eduardo Ospina

Eduardo Klein

Eduardo Portabella

 

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SWITTEST: Automatic Switch-Level Fault Simulation and Test Evaluation of Switched-Capacitor Systems., , , , и . DAC, стр. 281-286. ACM Press, (1997)Structural testing of pipelined analog to digital converters., , и . ISCAS (1), стр. 436-439. IEEE, (2001)Calibration of Capacitor Mismatch and Static Comparator Offset in SAR ADC with Digital Redundancy., , и . ISCAS, стр. 1-5. IEEE, (2020)Novel swapping technique for background calibration of capacitor mismatching in pipeline ADCS., , и . SBCCI, стр. 21-26. ACM, (2007)INL systematic reduced-test technique for Pipeline ADCs., , и . ETS, стр. 1-6. IEEE, (2014)Linearity test of high-speed high-performance ADCs using a self-testable on-chip generator., , , , , , и . ETS, стр. 1-6. IEEE, (2016)Statistical behavioral modeling and characterization of A/D converters., , и . ICCAD, стр. 562-566. IEEE Computer Society / ACM, (1995)Description of SAR ADCs with Digital Redundancy using a Unified Hardware-Based Approach., , , и . ISCAS, стр. 1-5. IEEE, (2018)Digital Background Calibration Technique for Pipeline ADCs with Multi-Bit Stages., , и . SBCCI, стр. 317-322. IEEE Computer Society, (2003)Mismatch and Offset Calibration in Redundant SAR ADC., , , и . DCIS, стр. 1-5. IEEE, (2019)