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Analysis and solution to overcome EOS failure induced by latchup test in a high-voltage integrated circuits., , , и . VLSI-DAT, стр. 1-4. IEEE, (2013)New design on 2×VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS process., и . VLSI-DAT, стр. 1-4. IEEE, (2012)Design of 2×VDD logic gates with only 1×VDD devices in nanoscale CMOS technology., и . SoCC, стр. 33-36. IEEE, (2013)Area-efficient power-rail ESD clamp circuit with SCR device embedded into ESD-transient detection circuit in a 65nm CMOS process., и . VLSI-DAT, стр. 1-4. IEEE, (2013)Interference of ESD protection diodes on RF performance in Giga-Hz RF circuits., и . ISCAS (1), стр. 297-300. IEEE, (2003)Electrostatic discharge protection circuits in CMOS IC's using the lateral SCR devices: an overview.. ICECS, стр. 325-328. IEEE, (1998)Circuit solutions on ESD protection design for mixed-voltage I/O buffers in nanoscale CMOS., и . CICC, стр. 689-696. IEEE, (2009)Design of 2xVDD-tolerant I/O buffer with 1xVDD CMOS devices., и . CICC, стр. 539-542. IEEE, (2009)Hardware/firmware co-design in an 8-bits microcontroller to solve the system-level ESD issue on keyboard., и . Microelectron. Reliab., 41 (3): 417-429 (2001)New Transient Detection Circuit for On-Chip Protection Design Against System-Level Electrical-Transient Disturbance., и . IEEE Trans. Ind. Electron., 57 (10): 3533-3543 (2010)