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Disambiguation of "Joardar, Biresh Kumar"

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Learning to Train CNNs on Faulty ReRAM-based Manycore Accelerators.

, , , , and . ACM Trans. Embed. Comput. Syst., 20 (5s): 55:1-55:23 (2021)

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Kamlesh Kumar

Surendra Kumar

Rohini Kumar

Pardeep Kumar

Aditya Kumar

 

Other publications of authors with the same name

Hybrid on-chip communication architectures for heterogeneous manycore systems., , , , and . ICCAD, page 62. ACM, (2018)NoC-enabled 3D Heterogeneous Manycore Systems for Big-Data Applications., , , and . ISQED, page 1-6. IEEE, (2022)3D NoC-Enabled Heterogeneous Manycore Architectures for Accelerating CNN Training: Performance and Thermal Trade-offs., , , , , , and . NOCS, page 18:1-18:8. ACM, (2017)High performance collective communication-aware 3D Network-on-Chip architectures., , and . DATE, page 1351-1356. IEEE, (2018)Attacking Memristor-Mapped Graph Neural Network by Inducing Slow-to-Write Errors., , , , and . ETS, page 1-4. IEEE, (2023)DARe: DropLayer-Aware Manycore ReRAM architecture for Training Graph Neural Networks., , , , and . ICCAD, page 1-9. IEEE, (2021)HeM3D: Heterogeneous Manycore Architecture Based on Monolithic 3D Vertical Integration., , , , , and . CoRR, (2020)Learning to Train CNNs on Faulty ReRAM-based Manycore Accelerators., , , , and . ACM Trans. Embed. Comput. Syst., 20 (5s): 55:1-55:23 (2021)Learning-based Application-Agnostic 3D NoC Design for Heterogeneous Manycore Systems., , , , , and . CoRR, (2018)FARe: Fault-Aware GNN Training on ReRAM-Based PIM Accelerators., , , , , and . DATE, page 1-6. IEEE, (2024)