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Algorithm/hardware co-optimized SAR image reconstruction with 3D-stacked logic in memory., , , , , and . HPEC, page 1-6. IEEE, (2014)Fully-digital oscillatory associative memories enabled by non-volatile logic., and . IJCNN, page 1-6. IEEE, (2013)Towards Hyperparameter-Agnostic DNN Training via Dynamical System Insights., , , , , and . CoRR, (2023)Hardware Redaction via Designer-Directed Fine-Grained eFPGA Insertion., , , , , and . DATE, page 1186-1191. IEEE, (2021)Design Automation Framework for Application-Specific Logic-in-Memory Blocks., , , , , and . ASAP, page 125-132. IEEE Computer Society, (2012)Unified power system analyses and models using equivalent circuit formulation., , , , and . ISGT, page 1-5. IEEE, (2016)A 3D-stacked logic-in-memory accelerator for application-specific data intensive computing., , , , , , and . 3DIC, page 1-7. IEEE, (2013)All-magnetic analog associative memory., and . NEWCAS, page 1-4. IEEE, (2013)Mismatch analysis and statistical design at 65 nm and below., , , , and . CICC, page 9-12. IEEE, (2008)A Systems Approach to Computing in Beyond CMOS Fabrics: Invited., , , , , , , , , and 2 other author(s). DAC, page 18:1-18:2. ACM, (2017)