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Thermal-Aware Task Scheduling for Energy Minimization in Heterogeneous Real-Time MPSoC Systems., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (8): 1269-1282 (2016)Application-level Studies of Cellular Neural Network-based Hardware Accelerators., , , , , and . CoRR, (2019)FeCAM: A Universal Compact Digital and Analog Content Addressable Memory Using Ferroelectric., , , , , , , and . CoRR, (2020)Seed-and-Vote based In-Memory Accelerator for DNA Read Mapping., , , , , and . ICCAD, page 56:1-56:9. IEEE, (2020)Improving Realistic Worst-Case Performance of NVCiM DNN Accelerators Through Training with Right-Censored Gaussian Noise., , , , and . ICCAD, page 1-9. IEEE, (2023)Computing-In-Memory Neural Network Accelerators for Safety-Critical Systems: Can Small Device Variations Be Disastrous?, , and . ICCAD, page 87:1-87:9. ACM, (2022)A Hybrid FeMFET-CMOS Analog Synapse Circuit for Neural Network Training and Inference., , , , , and . ISCAS, page 1-5. IEEE, (2020)Enhancing Hardware Security with Emerging Transistor Technologies., , , , , and . ACM Great Lakes Symposium on VLSI, page 305-310. ACM, (2016)System-level reliability modeling for MPSoCs., , , , and . CODES+ISSS, page 297-306. ACM, (2010)Cellular neural networks for image analysis using steep slope devices., , , , , and . ICCAD, page 92-95. IEEE, (2014)