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Fast and memory-efficient minimum spanning tree on the GPU.

, , and . Int. J. Comput. Sci. Eng., 8 (1): 21-33 (2013)

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Simulation methodology for timing analysis and design optimization in digital superconducting electronics., , , , , , and . ISQED, page 33-38. IEEE, (2022)Simulation and analysis of inductive impact on VLSI interconnects in the presence of process variations., , , , , and . CICC, page 309-312. IEEE, (2005)Measurement and characterization of pattern dependent process variations of interconnect resistance, capacitance and inductance in nanometer technologies., , , , , and . ACM Great Lakes Symposium on VLSI, page 14-18. ACM, (2006)A signal integrity-driven buffer insertion technique for post-routing noise and delay optimization., , , , , and . CICC, page 23-26. IEEE, (2002)A New Simulation Method for NBTI Analysis in SPICE Environment., , , , , , , , and . ISQED, page 41-46. IEEE Computer Society, (2007)Fast and memory-efficient minimum spanning tree on the GPU., , and . Int. J. Comput. Sci. Eng., 8 (1): 21-33 (2013)Technology CAD for competitive products., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 9 (11): 1209-1216 (1990)Accuracy and speed of real and complex interpolation., and . Computing, 11 (2): 147-158 (1973)