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110GHz Through-Silicon Via's Integrated in Silicon Photonics Interposers for Next-Generation Optical Modules., , , , , , , , , и . ECOC, стр. 1-4. IEEE, (2021)Cost effectiveness of 3D integration options., , и . 3DIC, стр. 1-6. IEEE, (2010)3D integration: Circuit design, test, and reliability challenges., , , , , , , , и . IOLTS, стр. 217. IEEE Computer Society, (2010)Collective die-to-wafer bonding enabling low-loss evanescent coupling for optically interconnected System-on-Wafer., , , , , , , , , и 7 other автор(ы). OFC, стр. 1-3. IEEE, (2024)Parameter Variation Effects on Timing Characteristics of High Performance Clocked Registers., и . PATMOS, том 3728 из Lecture Notes in Computer Science, стр. 508-517. Springer, (2005)Impact of 3D design choices on manufacturing cost., , , , и . 3DIC, стр. 1-5. IEEE, (2009)Active-lite interposer for 2.5 & 3D integration., , , , , , , , , и 5 other автор(ы). VLSIC, стр. 222-. IEEE, (2015)Effects of process and environmental variations on timing characteristics of clocked registers., и . ACM Great Lakes Symposium on VLSI, стр. 165-168. ACM, (2006)Highly Optimized O-band Si Ring Modulators for Low-Power Hybrid CMOS-SiPho Transceivers., , , , , , , , , и 7 other автор(ы). OFC, стр. 1-3. IEEE, (2023)Buffer sizing for delay uncertainty induced by process variations., , и . ICECS, стр. 415-418. IEEE, (2004)