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IACM: Integrated adaptive cache management for high-performance and energy-efficient GPGPU computing., , and . ICCD, page 380-383. IEEE Computer Society, (2016)MARF: A Memory-Aware CLFLUSH-Based Intra- and Inter-CPU Side-Channel Attack., , and . ESORICS (3), volume 14346 of Lecture Notes in Computer Science, page 120-140. Springer, (2023)HAP: A Heterogeneity-Conscious Runtime System for Adaptive Pipeline Parallelism., and . Euro-Par, volume 9833 of Lecture Notes in Computer Science, page 518-530. Springer, (2016)CoPart: Coordinated Partitioning of Last-Level Cache and Memory Bandwidth for Fairness-Aware Workload Consolidation on Commodity Servers., , and . EuroSys, page 10:1-10:16. ACM, (2019)Making nested parallel transactions practical using lightweight hardware support., , , and . ICS, page 61-71. ACM, (2010)Hypart: a hybrid technique for practical memory bandwidth partitioning on commodity servers., , , , and . PACT, page 5:1-5:14. ACM, (2018)Ased: availability, security, and debugging support usingtransactional memory., , , , , and . SPAA, page 366. ACM, (2008)HAPT: hardware-accelerated persistent transactions., and . NVMSA, page 1-6. IEEE, (2016)The OpenTM Transactional Application Programming Interface., , , , and . PACT, page 376-387. IEEE Computer Society, (2007)RMC: an integrated runtime system for adaptive many-core computing., , and . EMSOFT, page 13:1-13:10. ACM, (2016)