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Disambiguation of "Kurokawa, Atsushi"

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Accurate Method for Calculating the Effective Capacitance with RC Loads Based on the Thevenin Model.

, , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 92-A (10): 2531-2539 (2009)

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Atsushi Imai

Atsushi Imai

Atsushi Yagi

Atsushi Fukui

Atsushi Kambayashi

 

Other publications of authors with the same name

An effective model for evaluating vertical propagation delay in TSV-based 3-D ICs., , , , , , and . ISQED, page 519-523. IEEE, (2015)An analytical model of the overshooting effect for multiple-input gates in nanometer technologies., , , , and . ISCAS, page 1712-1715. IEEE, (2013)Cooling architectures using thermal sidewalls, interchip plates, and bottom plate for 3D ICs., , and . ISQED, page 283-288. IEEE, (2017)A simple yet precise capacitance estimation method for on-chip power delivery network towards EMC analysis., , , , , and . IEICE Electron. Express, 17 (14): 20200198 (2020)DEPOGIT: dense power-ground interconnect architecture for physical design integrity., , , and . ASP-DAC, page 517-522. IEEE Computer Society, (2004)Dummy Filling Methods for Reducing Interconnect Capacitance and Number of Fills., , , , , , , and . ISQED, page 586-591. IEEE Computer Society, (2005)Deep Neural Network Based Inductance Calculations of Wireless Power Transfer Systems., , , , and . GCCE, page 222-223. IEEE, (2022)Signal Propagation Delay Model in Vertically Stacked Chips., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 98-A (12): 2614-2624 (2015)Effective capacitance for gate delay with RC loads., , and . ISCAS (3), page 2795-2798. IEEE, (2005)Modeling of substrate contacts in TSV-based 3D ICs., , , , , , and . 3DIC, page 1-4. IEEE, (2014)