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Disambiguation of "Plana, Luis A."

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An admission control system for QoS provision on a best-effort GALS interconnect.

, , , and . ACSD, page 200-207. IEEE, (2008)

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Juliana Plana Borrás

Lara Planas Paz

Werner Luis

Emmanuel Planas

Pia Luislampe

 

Other publications of authors with the same name

Understanding the interconnection network of SpiNNaker., , , , and . ICS, page 286-295. ACM, (2009)Parallel Distribution of an Inner Hair Cell and Auditory Nerve Model for Real-Time Application., , , , and . IEEE Trans. Biomed. Circuits Syst., 12 (5): 1018-1026 (2018)Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems., , , , , , , , and . ISCAS, page 1-4. IEEE, (2017)Dynamic voltage and frequency scaling for neuromorphic many-core systems., , , , , , , , , and 9 other author(s). ISCAS, page 1-4. IEEE, (2017)Adaptive admission control on the SpiNNaker MPSoC., , and . SoCC, page 243-246. IEEE, (2009)Performance-driven syntax-directed synthesis of asynchronous processors., , , , and . CASES, page 43-47. ACM, (2007)An admission control system for QoS provision on a best-effort GALS interconnect., , , and . ACSD, page 200-207. IEEE, (2008)Architectural optimization for low-power nonpipelined asynchronous systems., and . IEEE Trans. Very Large Scale Integr. Syst., 6 (1): 56-65 (1998)Dynamic Power Management for Neuromorphic Many-Core Systems., , , , , , , , , and 5 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (8): 2973-2986 (2019)Optimizations for Very Long and Sparse Vector Operations on a RISC-V VPU: A Work-in-Progress., , , , , , , , and . ISC Workshops, volume 13999 of Lecture Notes in Computer Science, page 472-485. Springer, (2023)